Embodiments of the present invention relate to methods of reducing the overall dielectric constant in dielectric layers disposed on metallic interconnect structures, such as those used on semiconductor devices.
Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment is routinely used to produce devices having geometries as small as 28 nm and less, and new equipment designs are continually being developed and implemented to produce devices with even smaller geometries. As device geometries decrease, the impact of interconnect resistance and capacitance on device performance becomes more profound, limiting the performance of the device. To address these needs, metals such as aluminum and copper have been used for interconnects to decrease resistance, while the thickness of the dielectric layers surrounding the interconnects have been minimized to reduce capacitance. However, as the dielectric layer is thinned, its performance as a diffusion barrier to the underlying metal is diminished, resulting in decreased reliability of the device.